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rev. 4822b?ism?07/04 features 2.4-ghz radio transceiver operates in the unlicensed industrial, scientific, and medical (ism) band (2.4 ghz to 2.483 ghz) -95 dbm reception sensitivity up to 0 dbm output power range of up to 50 meters or more data throughput of up to 62.5 kbits/s highly integrated, low cost, minimal number of external components required dual dsss reconfigurable baseband correlators spi microcontroller interface (up to 2-mhz data rate) 13-mhz input clock operation low standby current < 1 a integrated 32-bit manufacturing id operating voltage from 2.7 v to 3.6 v operating temperature from -40 c to +85 c offered in a small footprint qfn48 package applications pc human interface devices ?mice ?keyboards ?joysticks peripheral gaming devices ? game controllers ? console keyboards general ? presenter tools ? remote controls ? consumer electronics ? barcode scanners ? pos peripherals ?toys functional description the atr2434 transceiver is a single-chip 2.4-ghz direct sequence spread spectrum (dsss) gaussian frequency shift keying (gfsk) baseband modem radio that con- nects directly to a microcontroller. wirelessusb ? 2.4-ghz dsss radio soc atr2434 preliminary
2 atr2434 [preliminary] 4822b?ism?07/04 figure 1. simplified block diagram pin configuration figure 2. pinning qfn48 serdes a serdes b dsss baseband a dsss baseband b digital synthesizer gfsk demodulator gfsk modulator ir q ss sck miso mosi reset pd dio dioval rfout rfin x13in x13 x13out nc nc nc nc rfout vcc nc nc vcc nc nc nc nc x13in pactl pd vcc nc nc vcc vcc nc x13out sck 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 atr2434 x 1 3 n c n c v c c n c v c c n c v c c r f i n n c n c v c c g n d v c c r e s e t n c n c n c m i s o i r q m o s i s s d i o d i o v a l
3 atr2434 [preliminary] 4822b?ism?07/04 pin description pin no. symbol type default function analog rf 46 rfin input input rf input. modulated rf signal received. 5 rfout output n/a rf output. modulated rf signal to be transmitted. crystal/power control 38 x13 input n/a crystal input (see section ?clocking and power management? on page 5). 35 x13in input n/a crystal input (see section ?clocking and power management? on page 5). 26 x13out output/hi-z output system clock. buffered 13-mhz system clock. 33 pd input n/a power down. asserting this input (low), will put the ic in the suspend mode (x13out is 0 when pd is low). 14 reset input n/a active low reset. device reset. 34 pactl i/o input pactl. external power amplifier control. pull-down or make output. serdes bypass mode communications/interrupt 20 dio i/o input data input/output. serdes bypass mode data transmit/receive. 19 dioval i/o input data i/o valid. serdes bypass mode data transmit/receive valid. 21 irq output/hi-z output irq. interrupt and serdes bypass mode dioclk. spi communications 23 mosi input n/a master-output-slave-input data. spi data input pin. 24 miso output/hi-z hi-z master-input-slave-output data. spi data output pin. 25 sck input n/a spi input clock. spi clock. 22 ss input n/a slave select enable. spi enable. power and ground 6, 9, 16, 28, 29, 32, 41, 42, 44, 45 vcc vcc h vcc = 2.7 v to 3.6 v. 13 gnd gnd l ground = 0 v. 1, 2, 3, 4, 7, 8, 10, 11, 12, 15, 17, 18, 27, 30, 31, 36, 37, 39, 40, 43, 47, 48 nc n/a n/a tie to ground. exposed paddle gnd gnd l must be tied to ground.
4 atr2434 [preliminary] 4822b?ism?07/04 applications support the atr2434 is supported by both the wirelessusb development kit and the wire- lessusb n:1 development kit. the development kit provides all of the materials and documents needed to cut the cord on multipoint to point and point to point low band- width high node density applications including four small form-factor sensor boards and a hub board that connect to wirelessusb rf module boards, comprehensive wire- lessusb protocol code examples and all of the associated schematics, gerber files and bill of materials. the wirelessusb n:1 development kit is also supported by the wire- lessusb listener tool. functional overview the atr2434 provides a complete wirelessusb spi to antenna radio modem. the atr2434 is designed to implement wireless devices operating in the worldwide 2.4-ghz industrial, scientific, and medical (ism) frequency band (2.400 ghz to 2.4835 ghz). it is intended for systems compliant with world-wide regulations covered by etsi en 301 489-1 v1.4.1, etsi en 300 328-1 v1.3.1 (european countries); fcc cfr 47 part 15 (usa and industry canada) and arib std-t66 (japan). the atr2434 contains a 2.4-ghz radio transceiver, a gfsk modem and a dual dsss reconfigurable baseband. the radio and baseband are both code- and frequency-agile. forty-nine spreading codes selected for opt imal performance (gold codes) are sup- ported across 78 1-mhz channels yielding a theoretical spectral capacity of 3822 channels. the atr2434 supports a range of up to 50 meters or more. 2.4-ghz radio the receiver and transmitter are a single-conversion low-intermediate frequency (low-if) architecture with fully integrated if channel matched filters to achieve high per- formance in the presence of interference. an integrated power amplifier (pa) provides an output power control range of 30 db in seven steps. both the receiver and transmitter integrated voltage controlled oscillator (vco) and synthesizer have the agility to cover the complete 2.4-ghz gfsk radio transmitter ism band. the vco loop filter is also integrated on-chip. gfsk modem the transmitter uses a dsp-based vector m odulator to convert the 1-mhz chips to an accurate gfsk carrier. the receiver uses a fully integrated frequency modulator (fm) detector with automatic data slicer to demodulate the gfsk signal. dual dsss baseband data is converted to dsss chips by a digital spreader. de-spreading is performed by an oversampled correlator. the dsss baseband cancels spurious noise and assembles properly correlated data bytes. the dsss baseband has four operating modes: 64 chips/bit single channel, 32 chips/bit dual channel, 32 chips/bit single channel 2 oversampled, and 32 chips/bit single channel dual data rate (ddr). 64 chips/bit single channel the baseband supports a single data stream operating at 15.625 kbits/s. the advantage of selecting this mode is its ability to tolera te a noisy environment. this is because the 15.625 kbits/s data stream utilizes the longest pn code resulting in the highest probabil- ity for recovering packets over the air. this mode can also be selected for systems requiring data transmissions over longer ranges.
5 atr2434 [preliminary] 4822b?ism?07/04 32 chips/bit dual channel the baseband supports two non-simultaneous data streams each operating at 31.25 kbits/s. 32 chips/bit single channel 2 oversampled the baseband supports a single data stream operating at 31.25 kbits/s that is sampled twice as much as the other modes. the advantage of selecting this mode is its ability to tolerate a noisy environment. 32 chips/bit single channel dual data rate (ddr) the baseband spreads bits in pairs and supports a single data stream operating at 62.5 kbits/s. serializer/deserializer (serdes) the atr2434 provides a data serializer/deserializer (serdes), which provides byte-level framing of transmit and receive data. bytes for transmission are loaded into the serdes and receive bytes are read from the serdes via the spi interface. the serdes provides double buffering of transmit and receive data. while one byte is being transmitted by the radio the next byte can be written to the serdes data register insuring there are no breaks in transmitted data. after a receive byte has been received it is loaded into the serdes data register and can be read at any time until the next byte is received, at which time the old contents of the serdes data register will be overwritten. application interfaces the atr2434 has a fully synchronous spi slave interface for connectivity to the applica- tion mcu. configuration and byte-oriented data transfer can be performed over this interface. an interrupt is provided to trigger real time events. an optional serdes bypass mode (dio) is provided for applications that require a syn- chronous serial bit-oriented data path. this interface is for data only. clocking and power management a 13-mhz crystal is directly connected to x13in and x13 without the need for external capacitors. the atr2434 has a programmable trim capability for adjusting the on-chip load capacitance supplied to the crystal. the radio frequency (rf) circuitry has on- chip decoupling capacitors. the atr2434 is powered from a 2.7 v to 3.6 v dc supply. the atr2434 can be shutdown to a fully static state using the pd pin. below are the requirements for the crystal to be directly connected to x13in and x13: nominal frequency: 13 mhz operating mode: fundamental mode resonance mode: parallel resonant frequency stability: 30 ppm series resistance: 100 ? load capacitance: 10 pf drive level: 10 w to 100 w
6 atr2434 [preliminary] 4822b?ism?07/04 receive signal strength indicator (rssi) the rssi register (reg 0x22) returns the relative signal strength of the on-channel signal power and can be used to: 1. determine the connection quality, 2. determine the value of the noise floor, and 3. check for a quiet channel before transmitting. the internal rssi voltage is sampled through a 5-bit analog-to-digital converter (adc). a state machine controls the conversion process. under normal conditions, the rssi state machine initiates a conversion when an on-channel carrier is detected and remains above the noise floor for over 50 s. the conversion produces a 5-bit value in the rssi register (reg 0x22, bits 4:0) along with a valid bit, rssi register (reg 0x22, bit 5). the state machine then remains in halt mode and does not reset for a new conversion until the receive mode is toggled off and on. once a connection has been established, the rssi register can be read to determine the relative connection quality of the channel. a rssi register value lower than 10 indicates that the received signal strength is low, a value greater than 28 indicates a strong signal level. to check for a quiet channel before transmitting, first set up the receive mode properly and read the rssi register (reg 0x22). if the valid bit is zero, then force the carrier detect register (reg 0x2f, bit 7 = 1) to initiate an adc conversion. then, wait a mini- mum of 50 s and read the rssi register again. next, clear the carrier detect register (reg 0x2f, bit 7 = 0) and turn the receiver off. measuring the noise floor of a quiet channel is inherently a noisy process so, for best results, this procedure should be repeated several times (~20) to compute an average noise floor level. a rssi register value of 0-10 indicates a channel that is relatively quiet. a rssi register value greater than 10 indicates the channel is probably being used. a rssi register value greater than 28 indicates the presence of a strong signal. application interfaces spi interface the atr2434 has a four-wire spi communication interface between an application mcu and one or more slave devices. the spi interface supports single-byte and multi- byte serial transfers. the four-wire spi co mmunications interface consists of master out-slave in (mosi), master in-slave out (miso), serial clock (sck), and slave select (ss ). the spi receives sck from an application mcu on the sck pin. data from the applica- tion mcu is shifted in on the mosi pin. data to the application mcu is shifted out on the miso pin. the active-low slave select (ss ) pin must be asserted to initiate an spi transfer. the application mcu can initiate an spi data transfer via a multi-byte transaction. the first byte is the command/address byte, and the following bytes are the data bytes as shown in table 1 on page 7 and figure 3 through figure 5 on page 7. the ss signal should not be deasserted between bytes. the spi communications is as follows: command direction (bit 7) = 0 enables spi read transaction. a 1 enables spi write transactions. command increment (bit 6) = 1 enables spi auto address increment. when set, the address field automatically increments at the end of each data byte in a burst access, otherwise the same address is accessed. six bits of address. eight bits of data.
7 atr2434 [preliminary] 4822b?ism?07/04 the spi communications interface has a burst mechanism, where the command byte can be followed by as many data bytes as desired. a burst transaction is terminated by deasserting the slave select (ss = 1). the spi communications interface single read and burst read sequences are shown in figure 3 and figure 4, respectively. the spi communications interface single write and burst write sequences are shown in figure 5 and figure 6 on page 8, respectively. figure 3. spi single read sequence figure 4. spi burst read sequence figure 5. spi single write sequence table 1. spi transaction format byte 1 byte 1 + n bit # 76[5:0][7:0] bit name dir inc address data ss mosi miso sck dir inc a0 a1 a2 a3 a4 a5 d0 d1 d2 d3 d4 d5 d6 d7 data to mcu addr cm d 00 ss mosi miso sck a0 a1 a2 a3 a4 a5 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 data to m cu 1 data to mcu 1+n addr cmd dir inc 01 ss mosi miso sck dir inc a0 a1 a2 a3 a4 a5 d0 d1 d2 d3 d4 d5 d6 d7 data from mcu addr cmd 10
8 atr2434 [preliminary] 4822b?ism?07/04 figure 6. spi burst write sequence dio interface the dio communications interface is an optional serdes bypass data-only transfer interface. in receive mode, dio and dioval are valid after the falling edge of irq, which clocks the data as shown in figure 7. in transmit mode, dio and dioval are sampled on the falling edge of the irq, which clocks the data as shown in figure 8. the application mcu samples the dio and dioval on the rising edge of irq. figure 7. dio receive sequence figure 8. dio transmit sequence ss mosi miso sck a0 a1 a2 a3 a4 a5 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 data from m cu 1 data from mcu 1+n addr cmd dir inc 11 dioval dio irq d7 d6 d5 d4 d3 d2 d... d14 d13 d12 d11 d10 d9 d8 d1 d0 data to mcu v7 v6 v5 v4 v3 v2 v... v14 v13 v12 v11 v10 v9 v8 v1 v0 dioval dio irq d7 d6 d5 d4 d3 d2 d... d14 d13 d12 d11 d10 d9 d8 d1 d0 data from mcu v7 v6 v5 v4 v3 v2 v... v14 v13 v12 v11 v10 v9 v8 v1 v0
9 atr2434 [preliminary] 4822b?ism?07/04 interrupts the atr2434 features three sets of interrupts: transmit, receive, and a wake interrupt. these interrupts all share a single pin (irq), but can be independently enabled/ disabled. in transmit mode, all receive interrupts are automatically disabled, and in transmit mode all receive interrupts are automatically disabled. however, the contents of the enable registers are preserved when switching between transmit and receive modes. interrupts are enabled and the status reads through 6 registers: receive interrupt enable (reg 0x07), receive interrupt status (reg 0x08), transmit interrupt enable (reg 0x0d), transmit interrupt status (reg 0x0e), wake enable (reg 0x1c), wake status (reg 0x1d). if more than 1 interrupt is enabled at any time, it is necessary to read the relevant inter- rupt status register to determine which event caused the irq pin to assert. even when a given interrupt source is disabled, the status of the condition that would otherwise cause an interrupt can be determined by reading the appropriate interrupt status register. it is therefore possible to use the devices without making use of the irq pin at all. firmware can poll the interrupt status register(s) to wait for an event, rather than using the irq pin. the polarity of all interrupts can be set by writing to the configuration register (reg 0x05), and it is possible to configure the irq pin to be open drain (if active low) or open source (if active high). wake interrupt when the pd pin is low, the oscillator is stopped. after pd is deasserted, the oscillator takes time to start, and until it has done so, it is not safe to use the spi interface. the wake interrupt indicates that the oscillator has started, and that the device is ready to receive spi transfers. the wake interrupt is enabled by setting bi t 0 of the wake enable register (reg 0x1c, bit 0 = 1). whether or not a wake interrupt is pending is indicated by the state of bit 0 of the wake status register (reg 0x1d, bit 0). reading the wake status register (reg 0x1d) clears the interrupt. transmit interrupts four interrupts are provided to flag the occurrence of transmit events. the interrupts are enabled by writing to the transmit interrupt enable register (reg 0x0d), and their status may be determined by reading the transmit interrupt status register (reg 0x0e). if more than 1 interrupt is enabled, it is necessary to read the transmit interrupt status register (reg 0x0e) to determine which event caused the irq pin to assert. the function and operation of these interrupts are described in detail in the section ?register descriptions? on page 10. receive interrupts eight interrupts are provided to flag the occurrence of receive events, four each for serdes a and b. in 64 chips/bit and 32 chips/bit ddr modes, only the serdes a interrupts are available, and the serdes b interrupts will never trigger, even if enabled. the interrupts are enabled by writing to the receive interrupt enable register (reg 0x07), and their status may be determined by reading the receive interrupt status register (reg 0x08). if more than one interrupt is enabled, it is necessary to read the receive interrupt status register (reg 0x08) to determine which event caused the irq pin to assert. the function and operation of these interrupts are described in detail in the section ?register descriptions? on page 10.
10 atr2434 [preliminary] 4822b?ism?07/04 register descriptions table 2 displays the list of registers inside the atr2434 that are addressable through the spi interface. all registers are read and writable, except where noted. table 2. register map (1) register name mnemonic address default access revision id reg_id 0x00 0x07 ro synthesizer a counter reg_syn_a_cnt 0x01 0x00 rw synthesizer n counter reg_syn_n_cnt 0x02 0x00 rw control reg_control 0x03 0x00 rw data rate reg_data_rate 0x04 0x00 rw configuration reg_config 0x05 0x01 rw serdes control reg_serdes_ctl 0x06 0x03 rw receive interrupt enable reg_rx_int_en 0x07 0x00 rw receive interrupt status reg_rx_int_stat 0x08 0x00 ro receive data a reg_rx_data_a 0x09 0x00 ro receive valid a reg_rx_valid_a 0x0a 0x00 ro receive data b reg_rx_data_b 0x0b 0x00 ro receive valid b reg_rx_valid_b 0x0c 0x00 ro transmit interrupt enable reg_tx_int_en 0x0d 0x00 rw transmit interrupt status reg_tx_int_stat 0x0e 0x00 ro transmit data reg_tx_data 0x0f 0x00 rw transmit valid reg_tx_valid 0x10 0x00 rw pn code reg_pn_code 0x11-0x18 0x1e8b6a3de0e9b222 rw threshold low reg_threshold_l 0x19 0x08 rw threshold high reg_threshold_h 0x1a 0x38 rw wake enable reg_wake_en 0x1c 0x00 rw wake status reg_wake_stat 0x1d 0x01 ro analog control reg_analog_ctl 0x20 0x04 rw channel reg_channel 0x21 0x00 rw receive signal strength indicator reg_rssi 0x22 0x00 ro power control reg_pa 0x23 0x00 rw crystal adjust reg_crystal_adj 0x24 0x00 rw vco calibration reg_vco_cal 0x26 0x00 rw agc control reg_agc_ctl 0x2e 0x00 rw carrier detect reg_carrier_detect 0x2f 0x00 rw clock manual reg_clock_manual 0x32 0x00 rw clock enable reg_clock_enable 0x33 0x00 rw synthesizer lock count reg_syn_lock_cnt 0x38 0x64 rw manufacturing id reg_mid 0x3c-0x3f - ro note: 1. all registers are accessed little endian.
11 atr2434 [preliminary] 4822b?ism?07/04 table 3. revision id register addr: 0x00 reg_id default: 0x07 76543210 silicon id product id bit name description 7:4 silicon id these are the silicon id revision bits. 0000 = rev a, 0001 = rev b, etc. these bits are read-only. 3:0 product id these are the product id revision bits. fixed at value 0111. these bits are read-only. table 4. synthesizer a counter addr: 0x01 reg_syn_a_cnt default: 0x00 76543210 reserved count bit name description 7:5 reserved these bits are reserved and should be written with zeros. 4:0 count the synthesizer a counter register is used for diagnostic purposes and is not recommended for normal operation. the channel register is the recommended method of setting the synthesizer frequency. the synthesizer a count along with the synthesizer n count can be used to generate the synthesizer frequency. the range of valid values of the synthesizer a count is 0 through 31. using the synthesizer a and n count register is an alternative to using the channel register. selection between the use of the channel register or the a and n registers is done through the channel register (reg 0x21, bit 7). when in channel mode the a and n count bits can be used to read the a and n values derived directly from the channel. table 5. synthesizer n counter addr: 0x02 reg_syn_n_cnt default: 0x00 76543210 reserved count bit name description 7 reserved this bit is reserved and should be written with zero. 6:0 count the synthesizer n counter register is used for diagnostic purposes and therefore is not recommended for normal operation. the channel register is the recommended method of setting the synthesizer frequency. the synthesizer n count along with the synthesizer a count can be used to generate the synthesizer frequency. the range of valid values of the synthesizer n count is 74 through 76. using the synthesizer a and n count register is an alternative to using the channel register. selection between the use of the channel register or the a and n registers is done through the channel register (reg 0x21, bit 7). when in channel mode the a and n count bits can be used to read the a and n values derived directly from the channel.
12 atr2434 [preliminary] 4822b?ism?07/04 table 6. control addr: 0x03 reg_control default: 0x00 76543210 rx enable tx enable pn code select auto syn count select auto pa disable pa enable auto syn disable syn enable bit name description 7 rx enable the receive enable bit is used to place the ic in receive mode. 1 = receive enabled 0 = receive disabled 6 tx enable the transmit enable bit is used to place the ic in transmit mode. 1 = transmit enabled 0 = transmit disabled 5 pn code select the pseudo-noise code select bit selects between the upper or lower half of the 64 chips/bit pn code. 1 = 32 most significant bits of pn code are used 0 = 32 least significant bits of pn code are used this bit applies only when the code width bit is set to 32 chips/bit pn codes (reg 0x04, bit 2 = 1). 4 auto syn count select the auto synthesizer count select bit is used to select the method of determining the settle time of the synthesizer. the two options are a programmable settle time based on the value in the syn lock count register (reg 0x38), in units of 2 s, or by the auto detection of the synthesizer lock. 1 = synthesizer settle time is based on a count in the syn lock count register (reg 0x38) 0 = synthesizer settle time is based on the internal synthesizer lock signal it is recommended that the auto syn count select bit is set to 1 as that guarantees a consistent settle time for the synthesizer. 3 auto pa disable the auto power amplifier disable bit is used to determine the method of controlling the power amplifier. the two options are automatically controlled by the baseband or by firmware through register writes. 1 = register controlled pa enable. 0 = auto pa enable when this bit is set to 1 the state of the pa enable is directly controlled by bit pa enable (reg 0x03, bit 2). it is recommended that this bit is set to 0 leaving the pa control to the baseband. 2 pa enable the pa enable bit is used to enable or disable the power amplifier. 1 = power amplifier enabled 0 = power amplifier disabled this bit only applies when the auto pa disable bit is selected (reg 0x03, bit 3 = 1), otherwise this bit is do not care . 1 auto syn disable the auto synthesizer disable bit is used to determine the method of controlling the synthesizer. the two options are automatic control by the baseband or by firmware through register writes. 1 = register controlled synthesizer enable 0 = auto synthesizer enable when this bit is set to 1 the state of the synthesizer is directly controlled by bit syn enable (reg 0x03, bit 0). when this bit is set to 0 the state of the synthesizer is controlled by the auto syn count select bit (reg 0x03, bit 4). it is recommended that this bit be set to 0 leaving the synthesizer control to the baseband. 0 syn enable the synthesizer enable bit is used to enable or disable the synthesizer. 1 = synthesizer enabled 0 = synthesizer disabled this bit only applies when auto syn disable bit is selected (reg 0x03, bit 1 = 1), otherwise this bit is do not care .
13 atr2434 [preliminary] 4822b?ism?07/04 table 7. data rate addr: 0x04 reg_data_rate default: 0x00 76543210 reserved code width data rate sample rate bit name description 7:3 reserved these bits are reserved and should be written with zeros. 2 (1) code width the code width bit is used to select between 32 chips/bit and 64 chips/bit pn codes. 1 = 32 chips/bit pn codes 0 = 64 chips/bit pn codes the number of chips/bit used impacts a number of factors such as data throughput, range and robustness to interference. by choosing a 32 chips/bit pn-code, the data throughput can be doubled or even quadrupled (when double data rate is set). a 64 chips/bit pn code offers improved range over its 32 chips/bit counterpart as well as more robustness to interference. by selecting to use a 32 chips/bit pn code a number of other register bits are impacted and need to be addressed. these are pn code select (reg 0x03, bit 5), data rate (reg 0x04, bit 1), and sample rate (reg 0x04, bit 0). 1 (1) data rate the data rate bit allows the user to select a double data rate mode of operation which delivers a raw data rate of 62.5 kbits/sec. 1 = double data rate - 2 bits per pn code (no odd bit transmissions) 0 = normal data rate - 1 bit per pn code this bit is applicable only when using 32 chips/bit pn codes which can be selected by setting the code width bit (reg 0x04, bit 2 = 1). when using the double data rate, the raw data throughput is 62.5 kbits/s because every 32 chips/bit pn code is interpreted as 2 bits of data. when using this mode a single 64 chips/bit pn code is placed in the pn code register. this 64 chips/bit pn code is then split into two and used by the baseband to offer the double data rate capability. when using the normal data rate, the raw data throughput is 32 kbits/sec. additionally, normal data rate enables the user to potentially correlate data using two differing 32 chips/bit pn codes. 0 (1) sample rate the sample rate bit allows the use of the 12 sampling when using 32 chips/bit pn codes and the normal data rate. 1 = 12 oversampling 0 = 6 oversampling using 12 oversampling improves the correlators receive sensitivity. when using 64 chips/bit pn codes or the double data rate this bit is do not care . when in the normal data rate setting and choosing 12 oversampling, eliminates the ability to receive from two different pn codes. therefore the only time when 12 oversampling is to be selected is when a 32 chips/bit pn code is being used and there is no need to receive data from sources with two different pn codes. note: 1. the following reg 0x04, bits 2:0 values are not valid: 001-not valid 010-not valid 011-not valid 111-not valid
14 atr2434 [preliminary] 4822b?ism?07/04 table 8. configuration addr: 0x05 reg_config default: 0x01 76543210 reserved receive invert tr a n s m i t invert reserved irq pin select bit name description 7:5 reserved these bits are reserved and should be written with zeros. 4 receive invert the receive invert bit is used to invert the received data. 1 = inverted over-the-air receive data 0 = non-inverted over-the-air receive data 3transmit invert the transmit invert bit is used to invert the data that is to be transmitted. 1 = inverted transmit data 0 = non-inverted transmit data 2 reserved this bit is reserved and should be written with zero. 1:0 irq pin select the interrupt request pin select bits are used to determine the drive method of the irq pin. 11 = open drain (asserted = 0, deasserted = hi-z) 10 = open source (asserted = 1, deasserted = hi-z) 01 = cmos (asserted = 1, deasserted = 0) 00 = cmos inverted (asserted = 0, deasserted = 1) table 9. serdes control addr: 0x06 reg_serdes_ctl default: 0x03 76543210 reserved serdes enable eof length bit name description 7:4 reserved these bits are reserved and should be written with zeros. 3 serdes enable the serdes enable bit is used to switch between bit-serial mode and serdes mode. 1 = serdes enabled 0 = serdes disabled, bit-serial mode enabled when the serdes is enabled data can be written to and read from the ic one byte at a time through the use of the serdes data registers. the bit-serial mode requires bits to be written one bit at a time through the use of the dio/dioval pins. it is recommended that the serdes mode be used to avoid the need to manage the timing required by the bit-serial mode. 2:0 eof length the end of frame length bits are used to set the number of sequential bit times for an inter-frame gap without valid data before an eof event is generated. when in receive mode and a valid bit has been received the eof event can then be identified by the number of bit times that expire without correlating any new data. the eof event causes data to be moved to the proper serdes data register and can also be used to generate interrupts. if 0 is the eof length, an eof condition will occur at the first invalid bit after a valid reception. table 10. receive interrupt enable addr: 0x07 reg_rx_int_en default: 0x00 76543210 underflow b overflow b eof b full b underflow a overflow a eof a full a
15 atr2434 [preliminary] 4822b?ism?07/04 bit name description 7 underflow b the underflow b bit is used to enable the interrupt associated with an underflow condition with the receive serdes data b register (reg 0x0b) 1 = underflow b interrupt enabled for receive serdes data b 0 = underflow b interrupt disabled for receive serdes data b an underflow condition occurs when attempting to read the receive serdes data b register (reg 0x0b) when it is empty. 6 overflow b the overflow b bit is used to enable the interrupt associated with an overflow condition with the receive serdes data b register (reg 0x0b) 1 = overflow b interrupt enabled for receive serdes data b 0 = overflow b interrupt disabled for receive serdes data b an overflow condition occurs when new received data is written into the receive serdes data b register (reg 0x0b) before the prior data is read out. 5 eof b the end of frame b bit is used to enable the interrupt associated with the channel b receiver eof condition. 1 = eof b interrupt enabled for channel b receiver 0 = eof b interrupt disabled for channel b receiver the eof irq asserts during an end of frame condition. end of frame conditions occur after at least one bit has been detected, and then the number of invalid bits in the frame exceeds the number in the eof length field. if 0 is the eof length, and eof condition will occur at the first invalid bit after a valid reception. this irq is cleared by reading the receive status register 4 full b the full b bit is used to enable the interrupt associated with the receive serdes data b register (reg 0x0b) having data placed in it. 1 = full b interrupt enabled for receive serdes data b 0 = full b interrupt disabled for receive serdes data b a full b condition occurs when data is transferred from the channel b receiver into the receive serdes data b register (reg 0x0b). this could occur when a complete byte is received or when an eof event occurs whether or not a complete byte has been received. 3 underflow a the underflow a bit is used to enable the interrupt associated with an underflow condition with the receive serdes data a register (reg 0x09) 1 = underflow a interrupt enabled for receive serdes data a 0 = underflow a interrupt disabled for receive serdes data a an underflow condition occurs when attempting to read the receive serdes data a register (reg 0x09) when it is empty. 2 overflow a the overflow a bit is used to enable the interrupt associated with an overflow condition with the receive serdes data a register (0x09) 1 = overflow a interrupt enabled for receive serdes data a 0 = overflow a interrupt disabled for receive serdes data a an overflow condition occurs when new receive data is written into the receive serdes data a register (reg 0x09) before the prior data is read out. 1 eof a the end of frame a bit is used to enable the interrupt associated with an end of frame condition with the channel a receiver. 1 = eof a interrupt enabled for channel a receiver 0 = eof a interrupt disabled for channel a receiver the eof irq asserts during an end of frame condition. end of frame conditions occur after at least one bit has been detected, and then the number of invalid bits in a frame exceeds the number in the eof length field. if 0 is the eof length, an eof condition will occur at the first invalid bit after a valid reception. this irq is cleared by reading the receive status register. 0 full a the full a bit is used to enable the interrupt associated with the receive serdes data a register (0x09) having data written into it. 1 = full a interrupt enabled for receive serdes data a 0 = full a interrupt disabled for receive serdes data a a full a condition occurs when data is transferred from the channel a receiver into the receive serdes data a register (reg 0x09). this could occur when a complete byte is received or when an eof event occurs whether or not a complete byte has been received.
16 atr2434 [preliminary] 4822b?ism?07/04 table 11. receive interrupt status addr: 0x08 reg_rx_int_stat default: 0x00 76543210 valid b flow violation b eof b full b valid a flow violation a eof a full a note: all status bits are set and readable in the registers regardless of irq enable status. this allows a polling scheme to be imple- mented without enabling irqs. the status bits are affected by the tx enable and rx enable (reg 0x03, bits 7:6). for example, the receive status will read 0 if the ic is not in receive mode. these register are read-only. bit name description 7 valid b the valid b bit is true when all the bits in the receive serdes data b register (reg 0x0b) are valid. 1 = all bits are valid for receive serdes data b 0 = not all bits are valid for receive serdes data b when data is written into the receive serdes data b register (reg 0x0b) this bit is set if all of the bits within the byte that has been written are valid. this bit cannot generate an interrupt. 6 flow violation b the flow violation b bit is used to signal whether an overflow or underflow condition has occurred for the receive serdes data b register (reg 0x0b). 1 = overflow/underflow interrupt pending for receive serdes data b 0 = no overflow/underflow interrupt pending for receive serdes data b overflow conditions occur when the radio loads new data into the receive serdes data b register (reg 0x0b) before the prior data has been read. underflow conditions occur when trying to read the receive serdes data b register (reg 0x0b) when the register is empty. this bit is cleared by reading the receive interrupt status register (reg 0x08) 5 eof b the end of frame b bit is used to signal whether an eof event has occurred on the channel b receive. 1 = eof interrupt pending for channel b 0 = no eof interrupt pending for channel b an eof condition occurs for the channel b receiver when receive has begun and then the number of bit times specified in the serdes control register (reg 0x06) elapse without any valid bits being received. this bit is cleared by reading the receive interrupt status register (reg 0x08) 4 full b the full b bit is used to signal when the receive serdes data b register (reg 0x0b) is filled with data. 1 = receive serdes data b full interrupt pending 0 = no receive serdes data b full interrupt pending a full b condition occurs when data is transferred from the channel b receiver into the receive serdes data b register (reg 0x0b). this could occur when a complete byte is received or when an eof event occurs whether or not a complete byte has been received. 3 valid a the valid a bit is true when all of the bits in the receive serdes data a register (reg 0x09) are valid. 1 = all bits are valid for receive serdes data a 0 = not all bits are valid for receive serdes data a when data is written into the receive serdes data a register (reg 0x09) this bit is set if all of the bits within the byte that has been written are valid. this bit cannot generate an interrupt. 2 flow violation a the flow violation a bit is used to signal whether an overflow or underflow condition has occurred for the receive serdes data a register (reg 0x09). 1 = overflow/underflow interrupt pending for receive serdes data a 0 = no overflow/underflow interrupt pending for receive serdes data a overflow conditions occur when the radio loads new data into the receive serdes data a register (reg 0x09) before the prior data has been read. underflow conditions occur when trying to read the receive serdes data a register (reg 0x09) when the register is empty. this bit is cleared by reading the receive interrupt status register (reg 0x08)
17 atr2434 [preliminary] 4822b?ism?07/04 1 eof a the end of frame a bit is used to signal whether an eof event has occurred on the channel a receive. 1 = eof interrupt pending for channel a 0 = no eof interrupt pending for channel a an eof condition occurs for the channel a receiver when receive has begun and then the number of bit times specified in the serdes control register (0x06) elapse without any valid bits being received. this bit is cleared by reading the receive interrupt status register (reg 0x08). 0 full a the full a bit is used to signal when the receive serdes data a register (reg 0x09) is filled with data. 1 = receive serdes data a full interrupt pending 0 = no receive serdes data a full interrupt pending a full a condition occurs when data is transferred from the channel a receiver into the receive serdes data a register (reg 0x09). this could occur when a complete byte is received or when an eof event occurs whether or not a complete byte has been received. table 12. receive serdes data a addr: 0x09 reg_rx_data_a default: 0x00 76543210 data bit name description 7:0 data received data for channel a. the over-the-air received order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3, followed by bit 4, followed by bit 5, followed by bit 6, followed by bit 7. this register is read-only. table 13. receive serdes valid a addr: 0x0a reg_rx_valid_a default: 0x00 76543210 valid bit name description 7:0 valid these bits indicate which of the bits in the receive serdes data a register (reg 0x09) are valid. a ?1? indicates that the corresponding data bit is valid for channel a. if the valid data bit is set in the receive interrupt status register (reg 0x08) all eight bits in the receive serdes data a register (reg 0x09) are valid. therefore, it is not necessary to read the receive serdes valid a register (reg 0x0a). the over-the-air received order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3, followed by bit 4, followed by bit 5, followed by bit 6, followed by bit 7. this register is read-only. table 14. receive serdes data b addr: 0x0b reg_rx_data_b default: 0x00 76543210 data bit name description 7:0 data received data for channel b. the over-the-air received order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3, followed by bit 4, followed by bit 5, followed by bit 6, followed by bit 7. this register is read-only.
18 atr2434 [preliminary] 4822b?ism?07/04 table 15. receive serdes valid b addr: 0x0c reg_rx_valid_b default: 0x00 76543210 valid bit name description 7:0 valid these bits indicate which of the bits in the receive serdes data b register (reg 0x0b) are valid. a ?1? indicates that the corresponding data bit is valid for channel b. if the valid data bit is set in the receive interrupt status register (0x08) all eight bits in the receive serdes data b register (reg 0x0b) are valid. therefore, it is not necessary to read the receive serdes valid b register (reg 0x0c).the over-the-air received order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3, followed by bit 4, followed by bit 5, followed by bit 6, followed by bit 7. this register is read-only. table 16. transmit interrupt enable addr: 0x0d reg_tx_int_en default: 0x00 76543210 reserved underflow overflow done empty bit name description 7:4 reserved these bits are reserved and should be written with zeros. 3 underflow the underflow bit is used to enable the interrupt associated with an underflow condition associated with the transmit serdes data register (reg 0x0f) 1 = underflow interrupt enabled 0 = underflow interrupt disabled an underflow condition occurs when attempting to transmit while the transmit serdes data register (reg 0x0f) does not have any data. 2 overflow the overflow bit is used to enabled the interrupt associated with an overflow condition with the transmit serdes data register (0x0f). 1 = overflow interrupt enabled 0 = overflow interrupt disabled an overflow condition occurs when attempting to write new data to the transmit serdes data register (reg 0x0f) before the preceding data has been transferred to the transmit shift register. 1 done the done bit is used to enable the interrupt that signals the end of the transmission of data. 1 = done interrupt enabled 0 = done interrupt disabled the done condition occurs when the transmit serdes data register (reg 0x0f) has transmitted all of its data and there is no more data for it to transmit. 0 empty the empty bit is used to enable the interrupt that signals when the transmit serdes register (reg 0x0f) is empty. 1 = empty interrupt enabled 0 = empty interrupt disabled the empty condition occurs when the transmit serdes data register (reg 0x0f) is loaded into the transmit buffer and it's safe to load the next byte
19 atr2434 [preliminary] 4822b?ism?07/04 table 17. transmit interrupt status addr: 0x0e reg_tx_int_stat default: 0x00 76543210 reserved underflow overflow done empty note: all status bits are set and readable in the registers regardless of irq enable status. this allows a polling scheme to be imple- mented without enabling irqs. the status bits are affected by the tx enable and rx enable (reg 0x03, bits 7:6). for example, the transmit status will read 0 if the ic is not in transmit mode. these registers are read-only. bit name description 7:4 reserved these bits are reserved. this register is read-only. 3 underflow the underflow bit is used to signal when an underflow condition associated with the transmit serdes data register (reg 0x0f) has occurred. 1 = underflow interrupt pending 0 = no underflow interrupt pending this irq will assert during an underflow condition to the transmit serdes data register (reg 0x0f). an underflow occurs when the transmitter is ready to sample transmit data, but there is no data ready in the transmit serdes data register (reg 0x0f). this will only assert after the transmitter has transmitted at least one bit. this bit is cleared by reading the transmit interrupt status register (reg 0x0e). 2 overflow the overflow bit is used to signal when an overflow condition associated with the transmit serdes data register (0x0f) has occurred. 1 = overflow interrupt pending 0 = no overflow interrupt pending this irq will assert during an overflow condition to the transmit serdes data register (reg 0x0f). an overflow occurs when the new data is loaded into the transmit serdes data register (reg 0x0f) before the previous data has been sent. this bit is cleared by reading the transmit interrupt status register (reg 0x0e). 1 done the done bit is used to signal the end of a data transmission. 1 = done interrupt pending 0 = no done interrupt pending this irq will assert when the data is finished sending a byte of data and there is no more data to be sent. this will only assert after the transmitter has transmitted as least one bit. this bit is cleared by reading the transmit interrupt status register (reg 0x0e) 0 empty the empty bit is used to signal when the transmit serdes data register (reg 0x0f) has been emptied. 1 = empty interrupt pending 0 = no empty interrupt pending this irq will assert when the transmit serdes is empty. when this irq is asserted it is ok to write to the transmit serdes data register (reg 0x0f). writing the transmit serdes data register (reg 0x0f) will clear this irq. it will be set when the data is loaded into the transmitter, and it is ok to write new data. note: 1. all status bits are set and readable in the registers regardless of irq enable status. this allows a polling scheme to b e implemented without enabling irqs. the status bits are affected by the tx enable and rx enable (reg 0x03, bits 7:6). for example, the transmit status will read 0 if the ic is not in transmit mode. these registers are read-only.
20 atr2434 [preliminary] 4822b?ism?07/04 table 18. transmit serdes data addr: 0x0f reg_tx_data default: 0x00 76543210 data bit name description 7:0 data transmit data. the over-the-air transmitted order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3, foll owed by bit 4, followed by bit 5, followed by bit 6, followed by bit 7. table 19. transmit serdes valid addr: 0x10 reg_tx_valid default: 0x00 76543210 valid bit name description 7:0 valid (1) the valid bits are used to determine which of the bits in the transmit serdes data register (reg 0x0f) are valid. 1 = valid transmit bit 0 = invalid transmit bit note: 1. the valid bit in the transmit serdes valid register (reg 0x10) is used to mark whether the radio will send data or pre- amble during that bit time of the data byte. data is sent lsb first. the serdes will continue to send data until there are no more valid bits in the shifter. for example, writing 0x0f to the transmit serdes valid register (reg 0x10) will send half a byte. table 20. pn code addr: 0x11-18 reg_pn_code default: 0x1e8b6a3de0e9b222 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 address 0x18 address 0x17 address 0x16 address 0x15 313029282726252423222120191817161514131211109876543210 address 0x14 address 0x13 address 0x12 address 0x11 bit name description 63:0 pn codes the value inside the 8 byte pn code register is used as the spreading code for dsss communication. all 8 bytes can be used together for 64 chips/bit pn code communication, or the registers can be split into two sets of 32 chips/bit pn codes and these can be used alone or with each other to accomplish faster data rates. not any 64 chips/bit value can be used as a pn code as there are certain characteristics that are needed to minimize the possibility of multiple pn codes interfering with each other or the possibility of invalid correlation. the over-the-air order is bit 0 followed by bit 1, followed by bit 62, followed by bit 63.
21 atr2434 [preliminary] 4822b?ism?07/04 table 21. threshold low addr: 0x19 reg_threshold_l default: 0x08 76543210 reserved threshold low bit name description 7 reserved this bit is reserved and should be written with zero. 6:0 threshold low the threshold low value is used to determine the number of missed chips allowed when attempting to correlate a single data bit of value 0. a perfect reception of a data bit of 0 with a 64 chips/bit pn code would result in zero correlation matches, meaning the exact inverse of the pn code has been received. by setting the threshold low value to 0x08 for example, up to eight chips can be erroneous while still identifying the value of the received data bit. this value along with the threshold high value determine the correlator count values for logic 1 and logic 0. the threshold values used determine the sensitivity of the receiver to interference and the dependability of the received data. by allowing a minimal number of erroneous chips the dependability of the received data increases while the robustness to interference decreases. on the other hand increasing the maximum number of missed chips means reduced data integrity but increased robustness to interference and increased range. table 22. threshold high addr: 0x1a reg_threshold_h default: 0x38 76543210 reserved threshold high bit name description 7 reserved this bit is reserved and should be written with zero. 6:0 threshold high the threshold high value is used to determine the number of matched chips allowed when attempting to correlate a single data bit of value 1. a perfect reception of a data bit of 1 with a 64 chips/bit or a 32 chips/bit pn code would result in 64 chips/bit or 32 chips/bit correlation matches, respectively, meaning every bit was received perfectly. by setting the threshold high value to 0x38 (64-8) for example, up to eight chips can be erroneous while still identifying the value of the received data bit. this value along with the threshold low value determine the correlator count values for logic 1 and logic 0. the threshold values used determine the sensitivity of the receiver to interference and the dependability of the received data. by allowing a minimal number of erroneous chips the dependability of the received data increases while the robustness to interference decreases. on the other hand increasing the maximum number of missed chips means reduced data integrity but increased robustness to interference and increased range.
22 atr2434 [preliminary] 4822b?ism?07/04 table 23. wake enable addr: 0x1c reg_wake_en default: 0x00 76543210 reserved wake-up enable bit name description 7:1 reserved these bits are reserved and should be written with zeros. 0 wake-up enable wake-up interrupt enable. 0 = disabled 1 = enabled a wake-up event is triggered when the pd pin is deasserted and once the ic is ready to receive spi communications. table 24. wake status addr: 0x1d reg_wake_stat default: 0x01 76543210 reserved wake-up status bit name description 7:1 reserved these bits are reserved. this register is read-only. 0 wake-up status wake-up status. 0 = wake interrupt not pending 1 = wake interrupt pending this irq will assert when a wake-up condition occurs. this bit is cleared by reading the wake status register (reg 0x1d). this register is read-only.
23 atr2434 [preliminary] 4822b?ism?07/04 table 25. analog control addr: 0x20 reg_analog_ctl default: 0x00 76543210 reserved agc disable mid read enable reserved reserved pa o u t p u t enable painv rst bit name description 7 reserved this bit is reserved and should be written with zero. 6 agc rssi control enables agc/rssi control via reg 0x2e and reg 0x2f. 5 mid read enable the mid read enable bit must be set to read the contents of the manufacturing id register (reg 0x3c-0x3f). enabling the manufacturing id register (reg 0x3c-0x3f) consumes power. this bit should only be set when reading the contents of the manufacturing id register (reg 0x3c-0x3f). 4:3 reserved these bits are reserved and should be written with zeros. 2pa output enable the power amplifier output enable bit is used to enable the pactl pin for control of an external power amplifier. 1 = pa control output enabled on pactl pin 0 = pa control output disabled on pactl pin 1 pa invert the power amplifier invert bit is used to specify the polarity of the pactl signal when the paoe bit is set high. pa output enable and pa invert cannot be simultaneously changed. 1 = pactl active low 0 = pactl active high 0 reset the reset bit is used to generate a self clearing device reset. 1 = device reset. all registers are restored to their default values 0 = no device reset table 26. channel addr: 0x21 reg_channel default: 0x00 76543210 a+n channel bit name description 7 a+n the a+n bit is used to specify whether the synthesizer frequency is generated through the use of the channel register (reg 0x21) or through the use of the synthesizer a counter register (reg 0x01) and the synthesizer n counter register (reg 0x02). 1 = synthesizer a counter register (reg 0x01) and the synthesizer n counter register (reg 0x02) registers used to generate synthesizer frequency 0 = channel register (reg 0x21) is used to generate synthesizer frequency when set to 1 the channel value is ignored and the values written in the synthesizer a counter register (reg 0x01) and the synthesizer n counter register (reg 0x02) are used. when set to 0 the values written to the synthesizer a counter register (reg 0x01) and the synthesizer n counter register (reg 0x02) are ignored and the channel value is used by the synthesizer. it is recommended that the channel register (reg 0x21) is used as opposed to the synthesizer a counter register (reg 0x01) and the synthesizer n counter register (reg 0x02) method. 6:0 channel the channel register (reg 0x21) is used to determine the synthesizer frequency when the a+n bit is set to 0. use of other channels may be restricted by certain regulatory agencies. a value of 1 corresponds to a communication frequency of 2.402 ghz, while a value of 79 corresponds to a frequency of 2.479 ghz. the channels are separated from each other by 1 mhz intervals.
24 atr2434 [preliminary] 4822b?ism?07/04 table 27. receive signal strength indicator (rssi) addr: 0x22 reg_rssi default: 0x00 76543210 reserved valid rssi note: the rssi will collect a single value each time the part is put into receive mode via control register (reg 0x03, bit 7 = 1 ). bit name description 7:6 reserved these bits are reserved. this register is read-only. 5 valid the valid bit indicates whether the rssi value in bits [4:0] are valid. this register is read only. 1 = rssi value is valid 0 = rssi value is invalid 4:0 rssi the receive strength signal indicator (rssi) value indicates the strength of the received signal. this is a read only value with the higher values indicating stronger received signals meaning more reliable transmissions. table 28. power control addr: 0x23 reg_pa default: 0x00 76543210 reserved pa bias bit name description 7:3 reserved these bits are reserved and should be written with zeros. 2:0 pa bias the power amplifier bias (pa bias) bits are used to set the transmit power of the ic through increasing (values up to 7) or decreasing (values down to 0) the gain of the on-chip power amplifier. the higher the register value the higher the transmit power. by changing the pa bias value signal strength management functions can be accomplished. for general purpose communication a value of 7 is recommended. table 29. crystal adjust addr: 0x24 reg_crystal_adj default: 0x00 76543210 reserved clock output disable crystal adjust bit name description 7 reserved this bit is reserved and should be written with zero. 6 clock output disable the clock output disable bit disables the 13 mhz clock driven on the x13out pin. 1 = no 13 mhz clock driven externally 0 = 13 mhz clock driven externally if the 13 mhz clock is driven on the x13out pin then receive sensitivity will be reduced by -4 dbm on channels 5+13n. by default the 13 mhz clock output pin is enabled. this pin is useful for adjusting the 13 mhz clock, but it interferes with every 13th channel beginning with 2.405 ghz channel. therefore, it is recommended that the 13 mhz clock output pin be disabled when not in use. 5:0 crystal adjust the crystal adjust value is used to calibrate the on-chip load capacitance supplied to the crystal. the crystal adjust value will depend on the parameters of the crystal being used. refer to the appropriate reference material for information about choosing the optimum crystal adjust value.
25 atr2434 [preliminary] 4822b?ism?07/04 table 30. vco calibration addr: 0x26 reg_vco_cal default: 0x00 76543210 vco slope enable reserved bit name description 7:6 vco slope enable (write-only) the voltage controlled oscillator (vco) slope enable bits are used to specify the amount of variance automatically added to the vco. 11 = -5/+5 vco adjust. the application mcu must configure this option during initialization 10 = -2/+3 vco adjust 01 = reserved 00 = no vco adjust these bits are undefined for read operations. 5:0 reserved these bits are reserved and should be written with zeros. table 31. agc control addr: 0x2e reg_agc_ctl default: 0x00 76543210 agc lock reserved bit name description 7 agc lock when set, this bit disables the on-chip lna agc system, powers down unused circuitry, and locks the lna to maximum gain. the user must set reg 20, bit 6 = 1 to enable writes to reg 0x2e. it is recommended this bit be set during initialization to save power. 6:0 reserved these bits are reserved and should be written with zeros. table 32. carrier detect addr: 0x2f reg_carrier_detect default: 0x00 76543210 carrier detect override reserved bit name description 7 carrier detect override when set, this bit overrides the carrier detect. the user must set reg 20, bit 6 = 1 to enable writes to reg 0x2f. 6:0 reserved these bits are reserved and should be written with zeros.
26 atr2434 [preliminary] 4822b?ism?07/04 table 33. clock manual addr: 0x32 reg_clock_manual default: 0x00 76543210 manual clock overrides bit name description 7:0 manual clock overrides this register must be written with 0x41 after reset for correct operation table 34. clock enable addr: 0x33 reg_clock_enable default: 0x00 76543210 manual clock enables bit name description 7:0 manual clock enables this register must be written with 0x41 after reset for correct operation table 35. synthesizer lock count addr: 0x38 reg_syn_lock_cnt default: 0x64 76543210 count bit name description 7:0 count determines the length of delay in 2 s increments for the synthesizer to lock when auto synthesizer is enabled via control register (0x03, bit 1 = 0) and not using the pll lock signal. table 36. manufacturing id addr: 0x3c-3f reg_mid 313029282726252423222120191817161514131211109876543210 address 0x3f address 0x3e address 0x3d address 0x3c bit name description 31:0 address[31:0] these bits are the manufacturing id (mid) for each ic. the contents of these bits cannot be read unless the mid read enable bit (bit 5) is set in the analog control register (reg 0x20). enabling the manufacturing id register (reg 0x3c-0x3f) consumes power. the mid read enable bit in the analog control register (reg 0x20, bit 5) should only be set when reading the contents of the manufacturing id register (reg 0x3c to 0x3f). this register is read-only.
27 atr2434 [preliminary] 4822b?ism?07/04 absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability . parameters pin symbol value unit storage temperature -65 to +150 c ambient temperature with power applied -55 to +125 c supply voltage on v cc relative to v ss -0.3 to +3.9 v dc voltage to logic inputs (1) -0.3 to v cc +0.3 v dc voltage applied to outputs in high-z state -0.3 to v cc +0.3 v static discharge voltage (digital) > 2000 v static discharge voltage (rf) (2) 500 v latch-up current +200, -200 ma notes: 1. it is permissible to connect voltages above v cc to inputs through a series resistor limiting input current to 1 ma. this cannot be done during power down mode. ac timing not guaranteed. 2. human body model (hbm). operating conditions parameters symbol value unit supply voltage v cc 2.7 to 3.6 v ambient temperature under bias t a -40 to +85 c ground voltage 0v oscillator or crystal frequency) f osc 13 mhz
28 atr2434 [preliminary] 4822b?ism?07/04 dc parameters description conditions symbol min. typ. (1) max. unit supply voltage v cc 2.7 3.0 3.6 v output high voltage condition 1 at i oh = -100.0 a v oh1 v cc - 0.1 v cc v output high voltage condition 2 at i oh = -2.0 ma v oh2 2.4 3.0 v output low voltage at i ol = 2.0 ma v ol 0.0 0.4 v input high voltage v ih 2.0 v cc (2) v input low voltage v il -0.3 +0.8 v input leakage current 0 < v in < v cc i il -1 0.26 +1 a pin input capacitance (except x13, x13in, rfin) c in 3.5 10 pf current consumption during power-down mode pd = low i sleep 0.24 10 a current consumption without synthesizer pd = high idle i cc 3ma i cc from pd high to oscillator stable startup i cc 1.8 ma average transmitter current consumption (3) no handshake tx avg i cc1 5.9 ma average transmitter current consumption (4) with handshaking tx avg i cc2 8.1 ma current consumption during receive rx i cc (peak) 57.7 ma current consumption during transmit tx i cc (peak) 69.1 ma current consumption with synthesizer on, no transmit or receive synth settle i cc 28.7 ma notes: 1. typical values measured with v cc = 3.0 v at 25 c. 2. it is permissible to connect voltages above v cc to inputs through a series resistor limiting input current to 1 ma. 3. average i cc when transmitting a 5-byte packet (3 data bytes + 2 bytes of protocol) every 10 ms using the wirelessusb 1-way protocol. 4. average i cc when transmitting a 5-byte packet (3 data bytes + 2 bytes of protocol) every 10 ms using the wirelessusb 2-way protocol.
29 atr2434 [preliminary] 4822b?ism?07/04 figure 9. spi timing diagram figure 10. spi burst read every 9th sck hi stretch timing diagram ac characteristics (1) : spi interface (3) description parameter min. typ. max. unit spi clock period t sck_cyc 476 ns spi clock high time t sck_hi (burst read) (2) 238 ns spi clock high time t sck_hi 158 ns spi clock low time t sck_lo 158 ns spi input data set-up time t dat_su 10 ns spi input data hold time t dat_hld 97 (3) ns spi output data valid time t dat_val 77 (3) 174 (3) ns spi slave select set-up time before first positive edge of sck (4) t ss_su 250 ns spi slave select hold time after last negative edge of sck t ss_hld 80 ns notes: 1. ac values are not guaranteed if voltages on any pin exceed v cc . 2. this stretch only applies to every 9 th sck hi pulse for spi burst reads only. 3. for f osc = 13 mhz, 3.3 v at 25 c. 4. sck must start low, otherwise the success of spi transactions are not guaranteed. data from m cu mosi t sck_cyc sck t sck_hi t sck_lo t dat_su t dat_hld miso ss t ss_su t ss_hld t dat_val data data s a m p l e d r i v e data from m cu data from mcu data to mcu data to mcu data to mcu miso t sck_cyc sck t sck_hi t sck_lo ss t dat_val data d r i v e data to mcu data to mcu every 8 th sck_hi every 9 th sck_hi every 10 th sck_hi t sck_hi (burst read) d r i v e d r i v e
30 atr2434 [preliminary] 4822b?ism?07/04 figure 11. dio receive timing diagram dio interface parameter description min. typ. max. unit transmit t tx_dioval_su dioval set-up time 2.1 s t tx_dio_su dio set-up time 2.1 s t tx_dioval_hld dioval hold time 0 s t tx_dio_hld dio hold time 0 s t tx_irq_hi minimum irq high time - 32 chips/bit ddr 8 s minimum irq high time - 32 chips/bit 16 s minimum irq high time - 64 chips/bit 32 s t tx_irq_lo minimum irq low time - 32 chips/bit ddr 8 s minimum irq low time - 32 chips/bit 16 s minimum irq low time - 64 chips/bit 32 s receive t rx_dioval_vld dioval valid time - 32 chips/bit ddr -0.01 +6.1 s dioval valid time - 32 chips/bit -0.01 +8.2 s dioval valid time - 64 chips/bit -0.01 +16.1 s t rx_dio_vld dio valid time - 32 chips/bit ddr -0.01 +6.1 s dio valid time - 32 chips/bit -0.01 +8.2 s dio valid time - 64 chips/bit -0.01 +16.1 s t rx_irq_hi minimum irq high time - 32 chips/bit ddr 1 s minimum irq high time - 32 chips/bit 1 s minimum irq high time - 64 chips/bit 1 s t rx_irq_lo minimum irq low time - 32 chips/bit ddr 8 s minimum irq low time - 32 chips/bit 16 s minimum irq low time - 64 chips/bit 32 s irq dio/ dioval t rx_irq_hi t rx_irq_lo t rx_dio_vld t rx_dioval_vld data s a m p l e s a m p l e data data
31 atr2434 [preliminary] 4822b?ism?07/04 figure 12. dio transmit timing diagram irq dio/ dioval t tx_irq_hi t tx_irq_lo t tx_dio_su t tx_dioval_su t tx_dio_hld t tx_dioval_hld data s a m p l e s a m p l e data radio parameters parameter description conditions min. typ. max. unit rf frequency range (1) 2.400 2.483 ghz radio receiver (v cc = 3.3 v, f osc = 13.000 mhz, x13out off, 64 chips/bit, threshold low = 8, threshold high = 56, ber < 10-3) sensitivity -85 -95 dbm maximum received signal -20 -6 dbm rssi value for pwrin > -40 dbm 28 - 31 rssi value for pwrin < -95 dbm 0 -10 interference performance co-channel interference rejection carrier-to-interference (c/i) c = -60 dbm 9 db adjacent (1 mhz) channel selectivity c/i 1 mhz c = -60 dbm -2 db adjacent (2 mhz) channel selectivity c/i 2 mhz c = -60 dbm -32 db adjacent (> 3 mhz) channel selectivity c/i > 3 mhz c = -67 dbm -40 db image (2) frequency interference, c/i image c = -67 dbm -31 db adjacent (1 mhz) interference to in-band image frequency, c/i image 1 mhz c = -67 dbm -38 db out-of-band blocking interference signal frequency 30 mhz to 2399 mhz except (fo/n and fo/n 1 mhz) (3) c = -67 dbm -24 dbm 2498 mhz to 12.75 ghz, except (fo/n and fo n 1 mhz) (3) c = -67 dbm -22 dbm intermodulation c = -64 dbm ? f = 5,10 mhz -31 dbm spurious emission 30 mhz to 1 ghz -57 dbm 1 ghz to 12.75 ghz except (4.8 ghz to 5.0 ghz) -47 dbm 4.8 ghz to 5.0 ghz -37 (4) dbm radio transmitter (v cc = 3.3 v, f osc = 13.000 mhz) maximum rf transmit power pa = 7 -0.5 dbm rf power control range 28.9 db notes: 1. subject to regulation. 2. image frequency is +4 mhz from desired channel (2 mhz low if, high side injection). 3. fo = tuned frequency, n = integer. 4. antenna matching network and antenna will attenuate the output signal at these frequencies to meet regulatory requirements.
32 atr2434 [preliminary] 4822b?ism?07/04 rf power range control step size seven steps, monotonic 4.1 db frequency deviation pn code pattern 10101010 276 khz frequency deviation pn code pattern 11110000 317 khz zero crossing eerror 80 ns occupied bandwidth 100-khz resolution bandwidth, -6 dbc 500 898 khz initial frequency offset 44.6 khz in-band spurious second channel power (2 mhz) -41 -30 dbm third channel power (>3 mhz) -49 -40 dbm non-harmonically related spurs 30 mhz to 12.75 ghz -57 dbm harmonic spurs second harmonic -20 dbm third harmonic -30 dbm fourth and greater harmonics -47 dbm radio parameters (continued) parameter description conditions min. typ. max. unit notes: 1. subject to regulation. 2. image frequency is +4 mhz from desired channel (2 mhz low if, high side injection). 3. fo = tuned frequency, n = integer. 4. antenna matching network and antenna will attenuate the output signal at these frequencies to meet regulatory requirements. power management timing parameter description conditions min. typ max. unit t pdn_x13 time from pd deassert to x13out 2000 s t spi_rdy time from oscillator stable to start of spi transactions 1 s t pwr_rst power on to reset deasserted v cc at 2.7 v 1300 s t rst minimum reset asserted pulse width 1 s t pwr_pd power on to pd deasserted (1) 1300 s t wake pd deassert to clocks running (2) 2000 s t pd minimum pd asserted pulse width 10 s t sleep pd assert to low power mode 50 s t wake_int pd deassert to irq (3) assert (wake interrupt) (4) 2000 s t stable pd deassert to clock stable to within 10 ppm 2100 s notes: 1. the pd pin must be asserted at power up to ensure proper crystal start-up. 2. when x13out is enabled. 3. both the polarity and the drive method of the irq pin are programmable. see page 14 for more details. figure 14 illustrates default values for the configuration register (reg 0x05, bits 1:0). 4. a wake-up event is triggered when the pd pin is deasserted. figure 14 illustrates a wake-up event configured to trigger an irq pin event via the wake enable register (reg 0x1c, bit 0 = 1).
33 atr2434 [preliminary] 4822b?ism?07/04 figure 13. power on reset/reset timing figure 14. sleep/wake timing ac test loads and waveforms for digital pins figure 15. ac test loads and waveforms for digital pins vcc reset pd x13out t pwr_rst t pwr_pd t spi_rdy t rst t pdn_x13 s t a r t u p irq x13out t wake_int t wake t pd t sleep pd s l e e p w a k e i r q t stable 90% 10% v cc gnd 90% 10% all input pulses output 30 pf including jig and scope output r th equivalent to: venin equivalent v th th rise time: 1 v/ns fall time: 1 v/ns output 5 pf including jig and scope max typical parameter unit r1 1071 ? r2 937 ? r th 500 ? v th 1.4 v v cc 3.00 v v cc output r1 r2 ac test loads dc test load
34 atr2434 [preliminary] 4822b?ism?07/04 package information ordering information extended type number package remarks atr2434-plq qfn48 - 7x7 taped and reeled ATR2434-TIQ so28 taped and reeled
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